A. Krishnamurthy, K. E. Schauser, C. J. Scheiman, R. Y. Wang,
D. E. Culler, K. A. Yelick.
Evaluation of Architectural Support for Global Address-Based
Communication in Large-Scale Parallel Machines.
Proc. Sixth International Conference on Architectural Support for
Programming Languages and Operating Systems.
pp. 258-267.
October 1996.
Also appeared as University of California Technical Report CSD-98-984.
Large-scale parallel machines are incorporating increasingly
sophisticated architectural support for user-level messaging and
global memory access. We provide a systematic evaluation of a broad
spectrum of current design alternatives based on our implementations
of a global address language on the Thinking Machine CM-5, Intel
Paragon, Meiko CS2, Cray T3D, and Berkeley NOW. This evaluation
includes a range of compilation strategies that make varying use of
the network processor; each is optimized for the target architecture
and the particular strategy. We analyze a family of interacting issues
that determine the performance tradeoffs in each implementation,
quantify the resulting latency, overhead, and bandwidth of the global
access operations, and demonstrate the effects on application
performance.